FPGA Hash Breaker

Github Link



I’ve just started this project, so not much to show yet. The goal is to brute force hashes using an unrolled, fully pipelined Verilog version of the MD5 hashing algorithm. If all goes well I’m looking at something in the range of 100 gigahashes per second, which blows CPU hashing out of the water. Maybe I’ll try to find a way to get it to integrate with hashcat or something, otherwise I’ll just write my own control software. The usage would be something like this:

-Create text file with brute forcing formats/character lists

-Create another text file full of the hashes

-Run command line C program that will transmit that data to the FPGA using UART

-FPGA will generate passwords, hash them, and compare to the given hashes.

-Send back any working hashes along with the original password that generated them.


Check back soon!